number, and position of the singular
factories is dependent on the physical
error rate and the size of the computation to be performed, and the type of
interconnects available. The space for
wiring is a surface code-dependent factor, not required when using other error
correction methods, and is probably a
substantial underestimate, though
researchers are currently looking for
compact compilations of programs on
the surface code that will minimize this
factor. The chosen code distance d is
strongly dependent on the application
algorithm itself and on the physical
gate error rate. Shor’s algorithm for L
= 2,048 demands that, roughly speaking, we must be able to run 1015 logical
operations with a high probability of
correctly executing them all. This work
was done assuming a physical error
rate of 0.2%, which is not very far below
the surface code threshold of 0.75%.
These two factors determine the large
distance of 56, and in the case of the
surface code required resources grow
as d2, giving the high scale-up factor.
The final factor of four is strongly dependent on the details of the microarchitecture and the yield.
This results in a final system size of
six billion physical qubits for the main
quantum state itself, each of which
must be independently controllable. In
this particular architecture, this staggering number must be augmented
with additional qubits for communications, on-chip optical switches, delay
lines, and many external supporting
lasers, optical switches, and measurement devices, all deployed in a large
The performance of the system is
determined by the error correction
time and the complexity of executing
the application gates on top of the error correction code. The surface code
cycle time on this architecture for measuring all error syndromes is ~50µsec,
far slower than the 100psec planned
for physical gates. A Toffoli gate will require ~50msec—a factor of 1,000 from
QEC cycle to logical gate, for this code
distance. Demonstrating how system-level issues affect performance, the
QEC cycle time is limited by contention for access to on-chip waveguides.
In part to address some of these ar-
chitectural limitations, the QuDOS ar-
chitecture was developed.
16 QuDOS, if
Large-scale designs are going to be
difficult to create and evaluate without
the appropriate tools. Further invest-
ment in automated tools for co-design
of internally heterogeneous hardware
and compilation of software is critical.
One good example of this practice is
Svore and Cross, working with Chuang,
who have developed tool chains with
round-trip engineering and error cor-
rection in mind.
Architectural analyses exist for ion
trap systems using Steane error correction, and multiple, distinct forms of
nanophotonic and solid-state systems
using the surface code.
7, 16, 26, 36 We next
take up one moderately complete architecture as an example.
An Architecture at scale
We can use error management and
application workloads to determine
the broad outlines of a computer that
could run a useful algorithm at full
scale. The size of a quantum computer
grows depending on the algorithm’s
demand for logical qubits, the quantum error correction scheme, the gate
and memory error rate, and other factors such as the yield of functional qubits in the system. Overall, including
space for various temporary variables
and the ancilla state distillation, the
scale-up factor from logical to physical qubits can reach half a million.
As a specific example, the resource
growth in one architecture36 can be assigned approximately as follows:
˲Establish a substantially post-classical goal of factoring an L=
2,048-bit number using Shor’s algorithm, requiring
˲ 6L logical qubits to run a time-effi-cient form of the algorithm, growing by
8 × to build “singular factories” for
the state distillation process, allowing
the algorithm to run at the speed of data,
1. 33 × to provide “wiring” room to
move logical qubits around within the
10, 000 × to run the Raussendorf-Harrington-Goyal form of the surface
code31 with an error correcting code
distance d = 56, and finally
4 × to work around a yield of functional devices of 40%.
A singular factory is simply a region
of the computer assigned by the programmer or compiler to the creation of
the ancillae discussed here. The size,
When will a
do science, rather
than be science?