shown to generate approximately 80%–90% of the code of a system. An initial prototype of a fully functional post-trade clearing system demonstrated that a

5k-line system description will generate up to 950k lines of C++, JavaScript, or SQL code.

Summary

The success of LSEG Technology bears testimony that despite contextual barriers, organizations in this region can indeed become globally competitive technology leaders in specialized niche markets. The early application of ‘creative disruption’ to a niche market with immense growth potential has proven to be a very effective tool and strategy.

The increasing pace of technological advancements warrant a balanced outlook toward agility, farsighted bets on technology, and investments in intellectual capital, to exploit the unfolding opportunities of the future. 1

References

1. Bloomberg LP U.S., 2019; https:// bloom.bg/2KG8NGl

2. Businesswire.com. 2013; http://bit.

ly/2R5Brlm

3. Finextra.com. 2016; http://bit.

ly/2wMtF6D

4. Fnlondon.com. 2016; http://bit.

ly/2K79sRC

5. Ibsintelligence.com. 2016; http://bit.

ly/2WyHC7w

6. London Stock Exchange Group PLC, U.K. 2019; https://www.lseg.com/ lseg-technology

7. Thomsonreuters.com. 2015; https:// tmsnrt.rs/2wNWvUg

8. Waterstechnology.com. 2017; http:// bit.ly/31pIsSV

9. Waterstechnology.com. 2018; http:// bit.ly/2wOLvpM

 

Ajit Samaranayake ( [e-mail]) is chief scientist at LSEG Technology, Colombo, Sri Lanka.

Sampath Tilakumara (sampath@lseg. com) is head of technology at LSEG Technology, Colombo, Sri Lanka.

Thayaparan Sripavan ( [e-mail]) is head of hardware-accelerated systems at LSEG Technology, Colombo, Sri Lanka. Rasika Withanawasam (rasikaw@lseg. com) is senior software architect at LSEG Technology, Colombo, Sri Lanka.

Copyright held by authors/owners.

ing hubs in London, Milan, Oslo, and Johannesburg.

2. and 3. High-performance and heterogeneous computing.

Execution of complex functionality at ultra-low latency is imperative for electronic trading systems.

That pattern of con-
founding expectations led
to a number of inflection
points when LSEG Technol-
ogy offered an ultra-low-
latency trading system to
address the London Stock
Exchange’s requirements in
2011. The low-latency exter-
nal interfaces developed as
part of this solution allowed
co-located high-frequency
traders to take advantage of
the ultra-low latency of the
platform. A sub 100µs step-
jump in end-to-end latency
was possible with a full-stack
re-architecture, and being
the first to infuse emerging
transport technologies (such
as Infiniband) helped the
London Stock Exchange gain
market share and stay ahead
of other leading exchanges.
In 2014, an award-win-
ning8, 9 low-latency market
data distribution platform
was introduced with the use
of field programmable gate
arrays (FPGA) 2 that yielded a
95% performance improve-
ment (sub 5µs end to end)
compared to homogeneous
software. 3–5, 7 The latest gen-
eration of the heterogeneous
(FPGA, GPU) application
suite enables new business
models by realizing financial
risk simulations and deep
learning in real time.
4. Description-driven
systems.
The description-driven
approach to software
generation was again a
disruptive response to meet
demands for higher quality
and quicker delivery, with
lower costs. LSEG Technol-
ogy introduced a patented
business rule engine
in 1998, which allowed
flexibility in specifying
business features without
requiring redeployment or
upgrades. The core of this
approach was extensible to
the description of an entire
system (that is, data model,
business functionality,
work flows, user interface
(UI), and deployment).
Using a combination of
theorem provers and code
generators, it has been

Distributed trading
system
Process pair
fault tolerance
Business rule
engine
Trading system
latency < 100µs
GPU accelerated
realtime risk
FPGA accelerated
market data
Smart systems (AI/ML)
Description driven systems
Domain specific hardware
Elastic Scalability

1 13

3 24

Future

2016 2009 1996 1998 1997 2002 2014

Figure 2. Themed milestones of creative disruption.

GW
G W: Access gateway
SEQ: Message sequencer
ME: Order matching
DS: Message distribution
MDS: Market data server
G W
(Replica)

Passive on line
fault tolerance
Active-active
fault tolerance
Software
process
Millennium Exchange Trading System

10 Giga bit/s
Ethernet link
Total transport
latency
Processing
partition
Infiniband links
Algorithms
SEQ
(Replica)

ME
ME
DS
DS
(Replica)

MDS
MDS
(Replica)

15 µs

6 µs

1. 5 µs

1 µs 1 µs 5 µs 3 µs X2 (in/out)

29 µs round trip G W to G W

Co-located
FPGA accelerated

Figure 3. An abstract view of the Millennium Exchange trading system.