ated for the Xerox Palo Alto Research Center in 1973. It was indeed the first personal computer, sporting the first bit-mapped display and first Ethernet local-area network. The device controllers for the novel display and network were microprograms stored in a 4,096- word × 32-bit WCS.

Microprocessors were still in the 8-bit era in the 1970s (such as the Intel 8080) and programmed primarily in assembly language. Rival designers would add novel instructions to outdo one another, showing their advantages through assembly language examples.

Gordon Moore believed Intel’s
next ISA would last the lifetime of
Intel, so he hired many clever com-
puter science Ph.D.’s and sent them
to a new facility in Portland to invent
the next great ISA. The 8800, as Intel
originally named it, was an ambi-
tious computer architecture project
for any era, certainly the most ag-
gressive of the 1980s. It had 32-bit
capability-based addressing, ob-
ject-oriented architecture, variable-
bit-length instructions, and its own
operating system written in the then-
new programming language Ada.

This ambitious project was alas several years late, forcing Intel to start an emergency replacement effort in Santa Clara to deliver a 16-bit microprocessor in 1979. Intel gave the new team 52 weeks to develop the new “8086” ISA and design and build the chip. Given the tight schedule, designing the ISA took only 10 person-weeks over three regular calendar weeks, essentially by extending the 8-bit registers and instruction set of the 8080 to 16 bits. The team completed the 8086 on schedule but to little fanfare when announced.

To Intel’s great fortune, IBM was developing a personal computer to compete with the Apple II and needed a 16-bit microprocessor. IBM was interested in the Motorola 68000, which had an ISA similar to the IBM 360, but it was behind IBM’s aggressive schedule. IBM switched instead to an 8-bit bus version of the 8086. When IBM announced the PC on August 12, 1981, the hope was to sell 250,000 PCs by 1986. The company instead sold 100 million worldwide, bestowing a very bright future on the emergency replacement Intel ISA.

Intel’s original 8800 project was renamed iAPX-432 and finally announced in 1981, but it required several chips and had severe performance problems. It was discontinued in 1986, the year after Intel extended the 16- bit 8086 ISA in the 80386 by expanding its registers from 16 bits to 32 bits. Moore’s prediction was thus correct that the next ISA would last as long as Intel did, but the marketplace chose the emergency replacement 8086 rather than the anointed 432. As the architects of the Motorola 68000 and iAPX- 432 both learned, the marketplace is rarely patient.

From complex to reduced instruc-
tion set computers. The early 1980s
saw several investigations into com-
plex instruction set computers (CISC)
enabled by the big microprograms in
the larger control stores. With Unix
demonstrating that even operating sys-
tems could use high-level languages,
the critical question became: “What in-
structions would compilers generate?”
instead of “What assembly language
would programmers use?” Significant-
ly raising the hardware/software inter-
ago still bring in $10 billion in rev-
enue per year.

As seen repeatedly, although the marketplace is an imperfect judge of technological issues, given the close ties between architecture and commercial computers, it eventually determines the success of architecture innovations that often require significant engineering investment.

Integrated circuits, CISC, 432, 8086, IBM PC. When computers began using integrated circuits, Moore’s Law meant control stores could become much larger. Larger memories in turn allowed much more complicated ISAs. Consider that the control store of the VAX-11/780 from Digital Equipment Corp. in 1977 was 5, 120 words × 96 bits, while its predecessor used only 256 words × 56 bits.

Some manufacturers chose to make microprogramming available by letting select customers add custom features they called “writable control store” (WCS). The most famous WCS computer was the Alto36 Turing laureates Chuck Thacker and Butler Lampson, together with their colleagues, cre-

Features of four models of the IBM System/360 family; IPS is instructions per second.

Model M30 M40 M50 M65 Datapath width 8 bits 16 bits 32 bits 64 bits Control store size 4k x 50 4k x 52 2.75k x 85 2.75k x 87 Clock rate (ROM cycle time)

1. 3 MHz (750 ns)

1. 6 MHz (625 ns)

2 MHz
(500 ns)
5 MHz
(200 ns)
Memory capacity 8–64 KiB 16–256 KiB 64–512 KiB 128–1,024 KiB
Performance (commercial) 29,000 IPS 75,000 IPS 169,000 IPS 567,000 IPS
Performance (scientific) 10,200 IPS 40,000 IPS 133,000 IPS 563,000 IPS
Price (1964 $) $192,000 $216,000 $460,000 $1,080,000
Price (2018 $) $1,560,000 $1,760,000 $3,720,000 $8,720,000

Figure 1. University of California, Berkeley, RISC-I and Stanford University MIPS microprocessors.