3. 4. Synthesis and back-end support
OpenPiton provides scripts to aid in synthesis and back-end physical design for generating realistic area results
or for manufacturing new chips based on OpenPiton.
The scripts are identical to the ones used to tape-out the
Piton processor, however the scripts have been made process agnostic and references to the specific technology
used have been removed due to proprietary foundry intellectual property concerns. Directions are included with
OpenPiton which describe how to port to a new foundry
kit. This allows the user to download OpenPiton, link to
the necessary process development kit files, and run our
full tool flow to produce the chip layout for a new instance
of OpenPiton. In this sense, OpenPiton is portable across
process technologies and provides a complete ecosystem
to implement, test, prototype, and tape-out (manufacture)
research chips.
4. APPLICATIONS
Table 2 presents a taxonomy of open source processors
which highlights important parameters for research. Since
OpenPiton’s first release in 2015, it has been used across a
wide range of applications and research domains, some of
which are described in this section.
the energy cost of differing operand values, and a confirmation of earlier results9 that showed that NoCs do not
dominate manycore processors’ power consumption.
Our study also produced what we believe is the most
detailed area breakdown of an open source manycore,
which we reproduce in Figure 6. All characterization data
from our study, as well as designs for the chip printed
circuit board (PCB), are now open source at http://www.
openpiton.org.
L1.5 Cache
7.62%
NoC1 Router
0.98%
NoC2 Router
0.95%
NoC3 Router
0.95%
FPU
2.64%
MITTS
0.17%
JTAG
0.10%
Config regs
0.05%
Core
47.00%
Clock tree
0.01%
Timing opt buffers
0.34%
Filler
16.32%
Unutilized
0.73%
Fetch
17.52%
Load/Store
22.33%
Execute
2.38%
Trap logic
6.42%
Multiply
1.53%
FP Front-end
1.85%
Config regs
0.11%
CCX Buffers
0.06% Clock tree
0.13%
Timing opt
buffers
3.83%
Filler
26.13%
Unutilized
0.90%
Tile0
3.27%Tile 1-24
78.37%
Chip bridge
0.12%
Clock circuitry
0.26% I/O cells
3.75%
ORAM
2.73% Timing opt
buffers
0.07%
Unutilized
2.12%
Tile Area: 1.17459 mm2 Core Area: .55205 mm2 Chip Area: 35.97552 mm2
Figure 6. Detailed area breakdown of Piton at chip, tile, and core
levels. Reproduced from McKeown et al. 13
Table 2. Taxonomy of differences of open source processors (table data last checked in April 2018).
Processor Architecture FPU OS MMU
HW
multi-
threaded
Multicore/
manycore/
GPU
Prototype
corecount NoC HDL
Back-end
scripts License
pAVR 8b AVR No – VHDL GPL v2
openMSP430 16bMSP430 No – Verilog BSD
CPU86 16bx86 No – VHDL GPL
Zet 16b x86 No – Verilog GPL v3
LatticeMico32 32bLatticeMico32 No – Verilog GPL
ZPU 32b MIPS No – VHDL FreeBSD & GPL
SecretBlaze 32b MicroBlaze No – VHDL GPL v3
AltOr32 32b ORBIS No – Verilog LGPL v3
aeMB 32b MicroBlaze No – Verilog LGPL v3
Amber 32b ARM v2a No – Verilog LGPL
OpenRISC 32b/64bORBIS No – Verilog LGPL
MIPS32 r1 32b MIPS32 r1 No – Verilog LGPL v3
LEON 3 32b SPARC V8 ($) SMP/AMP – VHDL GPL
OpenScale 32b MicroBlaze Manycore FPGA/6 VHDL GPL v3
XUM 32b MIPS32 r2 Manycore FPGA/8 Verilog LGPL v3
PicoRV32 32bRISC-V No FPGA/1 Verilog ISC
PULP-RI5CY 32b RISC-V Manycore Chip/9 SystemVerilog Solderpad 0.51
PULP-Zeroriscy 32b RISC-V Multicore Chip/1 SystemVerilog Solderpad 0.51
Nyuzi GPGPU Nyami ISA GPGPU FPGA SystemVerilog Apache 2.0
MIAOW GPGPU AMD Southern Islands GPU FPGA/1 Verilog BSD 3-Clause
OpTiMSoC 32b/64bORBIS Manycore FPGA/4 SystemVerilog MIT
Simply RISC S1 64b SPARC V9 No – Verilog GPL v2
BERI 64b MIPS/CHERI (BERI2) Multicore FPGA/4 Bluespec BERI HW-SW
OpenSPARC T1/T2 64b SPARC V9 Multicore Chip/8 Verilog GPL v2
Rocket 64b RISC-V Manycore Chip/8 Chisel BSD 3-Clause
AnyCore 64b RISC-V No Chip/1 SystemVerilog BSD 3-Clause
PULP-Ariane 64b RISC-V Manycore Chip/1 SystemVerilog Solderpad 0.51
BOOM 64b RISC-V Manycore FPGA Chisel BSD 3-Clause
OpenPiton 64b SPARC V9 Manycore Chip/25 Verilog BSD 3-Clause
& GPL v2
(RTOS)
