OpenPiton: An Open Source
Hardware Platform
For Your Research
By Jonathan Balkind, Michael McKeown, Yaosheng Fu, Tri Nguyen, Yanqi Zhou, Alexey Lavrov,
Mohammad Shahrad, Adi Fuchs, Samuel Payne, Xiaohua Liang, Matthew Matl, and David Wentzlaff
DOI: 10.1145/3366343
Abstract
Industry is building larger, more complex, manycore processors on the back of strong institutional knowledge,
but academic projects face difficulties in replicating that
scale. To alleviate these difficulties and to develop and
share knowledge, the community needs open architecture frameworks for simulation, chip design, and software
exploration that support extensibility, scalability, and configurability, alongside an established base of verification
tools and supported software. In this article, we present
OpenPiton, an open source framework for building scalable architecture research prototypes from one core to 500
million cores. OpenPiton is the world’s first open source,
general-purpose, multithreaded manycore processor, and
framework. OpenPiton is highly configurable, providing a
rich design space spanning a variety of hardware parameters that researchers can change. OpenPiton designs can be
emulated on FPGAs, where they can run full-stack multiuser
Debian Linux. OpenPiton is designed to scale to very large
core fabrics, enabling researchers to measure operating system, compiler, and software scalability. The mature codebase reflects the complexity of an industrial-grade design
and provides the necessary scripts to build new chips, making OpenPiton a natural choice for computer-aided design
(CAD) research. OpenPiton has been validated with a 25-core
chip prototype, named Piton, and is bolstered by a validation
suite that has thousands of tests, providing an environment
to test new hardware designs while verifying the correctness
of the whole system. OpenPiton is being actively used in
research both internally to Princeton and in the wider community, as well as being adopted in education, industry, and
government settings.
1. INTRODUCTION
Building processors for academic research purposes can be
a risky proposition. Particularly as processors have grown in
size, and with the focus on multicore and manycore proces-
sors, 17, 19, 20, 21, 14, 22, 6 the number of potential points of failure
in chip fabrication has increased drastically. To combat
this, the community needs well-tested, open-source, scal-
able frameworks that they can rely on as baselines to work
from and compare against. To reduce “academic time-to-
publication”, these frameworks must provide robust software
tools, mature full-system software stacks, rely on industry-
standard languages, and provide thorough test suites.
Additionally, to support research in a broad variety of fields,
The original version of this paper is entitled “OpenPiton:
An Open Source Manycore Research Framework” and was
published in Proceedings of ASPLOS 2016, Atlanta, GA,
April 2–6, 2016, ACM.
these frameworks must be highly configurable, be synthesiz-
able to FPGA and ASIC for prototyping purposes, and pro-
vide the basis for others to tape-out (manufacture) their own,
modified academic chips. Building and supporting such an
infrastructure is a major undertaking which has prevented
such prior designs. Our framework, OpenPiton, attacks this
challenge and provides all of these features and more.
OpenPiton is the world’s first open source, general-purpose, multithreaded manycore processor. OpenPiton is
scalable and portable; the architecture supports addressing for up to 500-million cores, supports shared memory
both within a chip and across multiple chips, and has been
designed to easily enable high performance 1000+ core
microprocessors and beyond. The design is implemented
in industry-standard Verilog HDL and does not require
the use of any new languages. OpenPiton enables research
from the small to the large with demonstrated implementations from the slimmed-down, single-core PicoPiton,
which is emulated on a $160 Xilinx Artix 7 at 29.5MHz,
up to the 25-core Piton processor which targeted a 1GHz
operating point and was recently validated and thoroughly
characterized. 12, 13
The OpenPiton platform shown in Figure 1 is a modern,
tiled, manycore design consisting of a 64-bit architecture
using the mature SPARC v9 ISA with P-Mesh: our scalable
cache coherence protocol and network on chip (NoC).
OpenPiton builds upon the industry-hardened, open-source
OpenSPARC T115, 1, 18 core, but sports a completely scratch-built uncore (caches, cache-coherence protocol, NoCs,
NoC-based I/O bridges, etc), a new and modern simulation
framework, configurable and portable FPGA scripts, a complete set of scripts enabling synthesis and implementation
of ready-to-manufacture chips, and full-stack multiuser
Debian Linux support. OpenPiton is available for download
at http://www.openpiton.org.
OpenPiton has been designed as a platform to enable
at-scale research. An explicit design goal of OpenPiton is
that it should be easy to use by other researchers. To support this, OpenPiton provides a high degree of integration
and configurability as shown in Table 1. Unlike many other
designs where the pieces are provided, but it is up to the