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ing of uniform vertical channels into
a wafer—or even all the way through
it. These channels are then filled with
metal to form “through-silicon vias”
(TSVs) that connect the top and bottom of a chip, “which helps the performance because you don’t have to convey the data to the edge of the chip,”
said Yamada. These methods resemble
the long-established “flip-chip” face-to-face bonding, but they can extend to
many chips.
Another key capability is thinning
of wafers to less than the thickness of
a human hair, which is useful both for
compact stacking and for facilitating
drilling holes through them. These
sheets, which may be as wide as an
entire wafer, then need to be precisely
aligned with and bonded to other processed circuits. Yamada notes that
reliably handling these thin layers,
often after temporarily gluing them
to another substrate for handling, is
in some ways “still a problem to be
solved,” although process engineers
have made significant progress.
Stacking also faces other challenges that make it expensive and have so
far limited its use. For one thing, the
modified structure requires significant changes in design. The array of
contacts throughout the active circuitry takes up significant real estate in
the middle of the chip that could otherwise be used for transistors. In ad-
FOR DECADES, INTEGRATED cir- cuits have been confined to a veneer on semiconductor chips, with transistors and wiring devices packed ever
more densely within this thin sheet. As
in-plane shrinkage has become more
challenging, however, electronics companies are looking to stack multiple
circuit layers vertically to boost speed
and functionality, while reducing power consumption and size.
“The performance of a system is not
controlled by the individual components, but by the way that you can assemble these different components,”
said Paolo Gargini, head of the International Roadmap for Devices and Systems, an IEEE Standards Association
Industry Connections program that has
supplanted the more device-focused
semiconductor roadmap. Over time,
stacking will give way to true monolithic
growth of three-dimensional (3D) chips
for some applications, like memory.
Historically, chips were electrically
connected with long, wide metal traces
on a printed circuit board, which take
a lot of energy and time to charge and
discharge. Engineers have long known
that stacking chips and connecting
them vertically improves both power
and speed by reducing the electrical
path between them. Memory technology has led the way in exploiting this
trick, but the potential benefits affect
everything from power-sensitive mobile devices to power-hungry processors in online data centers.
For high-performance computing,
“you can save 60%, 90% of the power required, because a lot of it is in communication from a processor and getting
access to the memory and doing the
compute locally,” said John Knickerbocker of IBM in Yorktown Heights, NY.
Stacking also compactly connects
chips made using incompatible pro-
cesses. At the International Electron
Devices Meeting in December, for ex-
ample, Sony reported sandwiching a
logic layer, a DRAM layer, and a CMOS
imaging layer in a stack that was only
130 microns thick.
A further advantage of combining
separate chips is that sensors “include
an analog circuit that prefers a higher
voltage in many cases. Logic circuits
prefer a lower voltage for power con-
sumption and speed,” said Fumiaki
Yamada, who worked on the Japanese
3D “Dream Chip” project exploring po-
tential technology for 3D chips, and is
now an independent consultant.
Stacking could also be the ultimate
way to pack diverse functions into
small devices like smart watches, or to
drive the nascent “Internet of Things”
(IoT). So far, however, many mobile
devices still use a more mature technology called package-on-package,
which stacks the chips only after they
have been packaged. The packages can
still be stacked vertically, and they are
equipped with an array of solder balls to
make many contacts to a common substrate, but the modularity allows manufacturers to design them independently
and test them before assembly.
Challenges
True 3D stacking exploits wafer-pro-cessing-style tools in service of packaging. One key element is deep etch-
Electronics Are
Leaving the Plane
Stacking chips and connecting them vertically
increases both speed and functionality.
Technology | DOI: 10.1145/3231207 Don Monroe
Artist’s representation of
integrated circuits stacked and
interconnected by through-chip vias.