at gigabytes per second, equivalent to
the speed of NAND flash. As such, the
error-correction hardware responsible
for encoding and decoding all reads
and writes to the flash is often the largest portion of the SSD controller. Some
controllers implement an error-cor-recting code (ECC) hardware engine
for every flash channel to improve parallel performance, while others implement a single ECC engine shared by all
the channels to reduce costs.
BCH. The most commonly used
ECC is Bose Chaudhuri Hocqueng-hem (BCH). It is preferred for its
speed and ease of implementation,
but this comes at the cost of ineffi-ciencies in the redundant storage required for ECC.
Flash-die designers make assumptions on the amount of BCH correctability needed for a given generation of
NAND flash and add redundant space
within each page and block to account for it. As dies have shrunk with
each successive generation of flash,
errors and the need for error correction have lifted; the minimum overhead required for correction (rather
than storage) has increased five times
over the past five years. In addition,
controller designs using BCH alone
historically assumed that bit failures
were uniform. Newer techniques offer more efficiency and correctability
based on better understanding of bit
failure characteristics and locality of
data within the NAND flash die.
LDPC. The use of low-density pari-ty-check (LDPC) code methods along
with more advanced information
from the NAND die has led to 8–10
times the correctability over previous
BCH methods. LDPC has some drawbacks, however: the correction performance is slower; it requires a significant amount of controller die space to
implement; and NAND die designers
are often reluctant to share information that would make the LDPC work
effectively, as the parametric data
needed is often considered a trade secret. A controller might include both
BCH and LDPC capability and use
LDPC only when the BCH techniques
fail, ensuring fast performance with
high data reliability.
XOR/Scramblers. Another novel
error-correction approach taken from
HDD arrays is using XOR parity across
nanD flash has
higher performance
but also a higher bit
error rate than other
storage media.
a group of NAND dies. This technique
should yield better correction with the
ability to survive a full NAND die failure. Also, a data scrambler is used to
“whiten” the data before it is written
to the die. Whitening the data protects
against writing certain user data patterns to the NAND die that can cause
high bit failures that result from adjacent interference between cells in the
memory array.
controller firmware
An SSD essentially has a complex file
system running internally on the controller. The firmware running this file
system is one of the key differentiators
among different SSDs today.
Mapping blocks. The primary function of the flash translation layer (FTL)
is to map logical blocks from the
system to physical NAND pages and
blocks. This mapping has the challenge of handling multiple sizes of requests and alignments because of the
asymmetrical I/O access limitations
of NAND flash. The system uses logical blocks consisting of 512 bytes or
4KB, which then get mapped into 8KB
NAND pages, and finally must be written into a block consisting of 64 or 128
pages.
SSDs have no standard technique
for overcoming this issue. A common
method is statically to map contiguous
logical blocks into page-aligned allocation units the size of the NAND page.
Once the SSD has enough written allocation units, they are combined into
a NAND block-size unit before being
written to the flash. Most SSDs today
use a derivative of the log-structured
file system (LFS) as the basis for the
FTL because the append-only write
design works well as a result of the
erase-before-programming limitation
of NAND flash.
Garbage collection. Because writes
can be written only to empty blocks,
the FTL must maintain a pool of free
blocks. If the FTL runs out of free
NAND blocks, or if the SSD is inactive
for a period of time, the firmware starts
performing background garbage-col-lection operations to reclaim sparsely filled NAND blocks. These NAND
blocks are reclaimed by merging the
data into new blocks and erasing the
old blocks, thus creating a pool of free
blocks for use by the FTL.