Casting off the tyranny of the clock offers freedom to optimize the separate parts of a design. For example, Rajit Manohar and his students at Cornell report a clock-free IEEE-com-pliant, double precision, floating-point adder with the same throughput as an equivalent clocked design. The Cornell clock-free design uses less than half, about 40%, as much energy per addition as its clocked counterpart. The Cornell design gains simplicity and thus reduces energy by doing easy cases fast and allowing the rare hard cases to take longer. A recent paper from my group in the Asynchronous Research Center at Portland State University reports on faster division by allowing steps that merely shift to go faster than steps that must subtract.

Casting off the tyranny of the clock offers modularity as well as local optimization. Sam Fuller, then chief engineer at Digital Equipment Corporation, once told me that his process people could provide faster chips every six months. He complained that his product could not similarly improve every six months because it took 18 months to redesign an entire computer for the new clock speed. The tyranny of the clock made his design insufficiently modular to permit incremental improvement. He chose to march his entire machine to a single drumbeat rather than allowing each part to work at its own best speed.

Like all tyranny, the tyranny of the clock stems from the range over which we choose to subject ourselves to the tyrant’s authority.

The clock-free paradigm I promote relates to the clocked design paradigm as a “free economy” relates to a “ controlled economy.” We can regain the efficiency of local decision making by revolting against the pervasive beat of an external clock.

Clock-free commercial products are in use today. Handshake Solutions, a computer-aided design company from the Netherlands, was proud of having 700 million of their clock-free chips in use in smart cards, passports, cell-phones, and other portable devices. Fulcrum Microsystems, a Caltech spin-off recently purchased by Intel, sells a self-timed communication switch with outstanding performance.

Casting off the
tyranny of the clock
offers freedom to
optimize the separate
parts of a design.

The paradigm shift I seek faces
three formidable obstacles: techni-
cal, social and courage. First, tech-
nical: Make no mistake; designing a
clock-free system can face the same
hard problems of parallelism that
give software people nightmares. But
a few pioneers have shown that clock-
free design is possible and sometimes
even easy. The pioneers have uncov-
ered benefits like using less than half,
40%, of the energy per operation as
reported by Cornell. Second, social:
All of today’s commercial design tools
assume clocked design. All engineer-
ing schools teach clocked design. Will
we ever train enough young people in
the clock-free paradigm for it to self-
perpetuate? Third, courage: Manage-
ment knows the costs, difficulties,
and results of the “tried and true”
clocked design paradigm. Manage-
ment chooses “to bear those ills we
have rather than fly to others that we
know not of.”
The clock-free design paradigm
must eventually prevail. It fits phys-
ics. Each increase in the relative cost
of communication over logic brings
us closer to the fundamental physi-
cal truth that “simultaneous” lacks
meaning. The clock-free paradigm
fits everything we have learned since
Turing about programming. Software
avoids tyrannous global time con-
straints. Without freedom from glob-
al time constraints, software libraries
would be impossible. “Modularity”
and “data hiding” are basic principles
of quality software because they allow
reuse and local optimization. Soft-
ware is self-timed: Each subroutine
runs at its own pace; its users wait for
it to finish. Imagine what software
would be like if subroutines could
start and end only at preset time in-
tervals. “My subroutines all start at
3. 68 millisecond intervals; how often
do yours start?”
Software development proceeds
from correctness to performance. Af-
ter software works, we tune its heavily
used parts to achieve the desired per-
formance. Performance almost always
depends on only a small part of the
whole. Compare this to the situation
in a clocked hardware design where
each and every signal must arrive “on
time,” even if it is rarely used. The
tyranny of the clock wastes both engi-
neering cost at design time and energy
at runtime. What a needless waste!

this Viewpoint is derived from Ivan sutherland’s presentation at the aCM a.M. turing Centenary Celebration Computer architecture panel discussion this past June; see http://amturing.acm.org/acm_tcc_webcasts.cfm. [also see the profile of Ivan sutherland in the news section of this issue on page 10. —Ed.]

Further Reading Sutherland, I.E. Micropipelines. Commun. ACM 32, 6 (June 1989). Sutherland, I.E. and Ebergen, J. Computers without clocks. Scientific American 287, 2 (Aug. 2002), 62–69.

Riaz Sheikh and R. Manohar.
An operand-optimized asynchronous IEEE
754 double-precision floating-point adder.
In Proceedings of the IEEE International
Symposium on Asynchronous Circuits and
Systems (ASYNC) 2010, 151–162.
N. Jamadagni and J. Ebergen.
An asynchronous divider implementation.
In Proceedings of the IEEE International
Symposium on Asynchronous Circuits and
Systems (ASYNC), 2012.

Ivan Sutherland ( [e-mail]) is a visiting scientist in the asynchronous research Center at Portland state university in oregon and the 1988 recipient of the aCM a. M. turing award for his pioneering contributions to computer graphics.