is conservative. PCM subsystems would more likely experience a mix of compute and memory-intensive workloads.
Expected lifetimes would be higher had we considered, for
example, single-threaded SPEC integer workloads. However,
such workloads are less relevant for a study of memory subsystems. Moreover, within memory-intensive workloads, we
would expect to see a mix of read and write intensive applications, which may further increase lifetimes.
Scalability is projected to improve PCM endurance
from the present 1E+08 to 1E+ 12 writes per bit at 32nm
with known manufacturable solutions. 17 This higher
endurance increases lifetime by four orders of magnitude in our models. ITRS anticipates 1E+ 15 PCM writes
at 22nm although manufacturable solutions are currently
The proposed memory architecture lays the foundation
for exploiting PCM scalability and nonvolatility in main
memory. Scalability implies lower main memory energy
and greater write endurance. Furthermore, nonvolatile
main memories will fundamentally change the landscape
of computing. Software cognizant of this newly provided
persistence can provide qualitatively new capabilities. For
example, system boot/hibernate will be perceived as instantaneous; application checkpointing will be inexpensive7; file
systems will provide stronger safety guarantees. 6 Thus, we
take a step toward a new memory hierarchy with deep implications across the hardware–software interface.
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university of Rochester.
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Onur Mutlu ( email@example.com), Carnegie
Doug Burger ( firstname.lastname@example.org),
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