figure 1. Phase change memory. (a) storage element with heating resistor and chalcogenide between electrodes. (b) cell structure with storage element and BJt access device. (c) Reset to an amorphous, high resistance state with a high, short current pulse. set to a crystalline, low resistance state with moderate, long current pulse. slope of set current ramp down determines the state in mLc.

Bitline
Heater Metal (access) Wordline Access dev Storage SET ISET tSET,MLC tSET,SLC t IRESETI

Metal (bitline)

Chalcogenide

RESET
tRESET
(a)

(b)

(c)

2. Pcm technoLoGY Given the still speculative state of PCM technology, researchers have made several different manufacturing and design decisions. We survey device and circuit prototypes published within the last 5 years. 10

2. 1. memory cell

As shown in Figure 1a, the PCM storage element is comprised of two metal electrodes separated by a resistive heater and a chalcogenide, the phase change material. Ge2Sb2Te5 (GST) is most commonly used, but other chalcogenides may offer higher resistivity and improve the device’s electrical characteristics. Nitrogen doping increases resistivity and lowers programming current while GS may offer faster phase changes. 4, 8

As shown in Figure 1b, PCM cells are 1T/1R devices, comprised of the resistive storage element and an access transistor. Access is typically controlled by one of three devices: field-effect transistor (FET), bipolar junction transistor (BJT), or diode. In future, FET scaling and large voltage drops across the cell may adversely affect reliability for unselected wordlines. 14 BJTs are faster and expected to scale more robustly without this vulnerability. 3, 14 Diodes occupy smaller areas and potentially enable greater cell densities, but require higher operating voltages. 11

Phase changes are induced by injecting current into the resistor junction and heating the chalcogenide. Current and voltage characteristics of the chalcogenide are identical regardless of its initial phase, which lowers programming complexity and latency. 9 The amplitude and width of the injected current pulse determine the programmed state as shown in Figure 1c.

2. 2. operation

The access transistor injects current into the storage material and thermally induces phase change, which is detected as a programmed resistance during reads. Logical data values are captured by the resistivity of the chalcogenide. A high, short current pulse increases resistivity by abruptly discontinuing current, quickly quenching heat generation, and freezing the chalcogenide into an amorphous state (i.e., reset). A moderate, long current pulse reduces resistivity by ramping down current, gradually cooling the chalcogenide,

and inducing crystal growth (i.e., set). Requiring longer current pulses, set latency determines write performance. Requiring higher current pulses, reset energy determines write power.

Prior to reading the cell, the bitline is precharged to the read voltage. If a selected cell is in a crystalline state, the bitline is discharged with current flowing through the storage element and access transistor. Otherwise, the cell is in an amorphous state, preventing or limiting bitline current.

Cells that store multiple resistance levels might be implemented by leveraging intermediate states, in which the chalcogenide is partially crystalline and partially amorphous. 3, 13 Smaller current slopes (i.e., slow ramp down) produce lower resistances and larger slopes (i.e., fast ramp down) produce higher resistances. Varying slopes induce partial phase transitions changing the size or shape of the amorphous material produced at the contact area, giving rise to resistances between those observed from the fully amorphous or the fully crystalline chalcogenide. The difficulty and high latency of differentiating between a large number of resistances may constrain such multilevel cells (MLC) to a small number of bits per cell.

wear and endurance: Writes are the primary wear mechanism in PCM. When injecting current into a volume of phase change material, thermal expansion and contraction degrades the electrode-storage contact, such that programming currents are no longer reliably injected into the cell. Since material resistivity is highly dependent on current injection, current variability causes resistance variability. This greater variability degrades the read window, the difference between programmed minimum and maximum resistance.

Write endurance, the number of writes performed before the cell cannot be programmed reliably, ranges from 1E+04 to 1E+09. Write endurance depends on process and differs across manufacturers. Relative to Flash, PCM is likely to exhibit greater write endurance by at least two to three orders of magnitude; Flash cells can sustain only 1E+05 writes. The ITRS roadmap projects improved endurance of 1E+ 12 writes at 32nm. 17 With wear reduction and leveling techniques, PCM write limits may not be exposed to the system during a memory’s lifetime.