Doi: 10.1145/1785414.1785440
technical Perspective
technology scaling
Redirects main memories
By Mary Jane Irwin
as prediCTed b Y Intel’s Gordon Moore in
1965, based on his observation of the
scaling of several generations of silicon
technology at the time, the number of
transistors that can be integrated on
one die continues to double approximately every two years. Amazing to
some, Moore’s Law has prevailed for
45 years and is expected to continue for
several more generations. Transistor
feature size and die integration capacity projections from the International
Technology Roadmap for Semiconductors (ITRS) roadmap is shown in
the accompanying table here.
These faster and more abundant
transistors have been exploited by
computer engineers to build processors that double in performance about
every two years. Up until the beginning
of this decade, that was done through
faster clock speeds and clever architectural enhancements. Many of these
architectural enhancements were directed at tackling the “memory wall,”
which still plagues us today. Early in
this decade, we ran into the “power
wall” that dramatically slowed the increase in clock speeds. Since then, we
are still seeing performance doublea
every two years, but now it’s through
having more cores (running at only
modestly faster clock rates) on one die
since technology scaling provides all
of those additional transistors.
Another key component on the
motherboard affected by technology
scaling is the main memory, traditionally built out of dynamic random access memory (DRAM) parts. DRAMs
have been doubling in capacity every
two to three years while their access latency has improved about 7% per year.
However, processors speeds still leave
main memories in the dust—with the
processors having to wait 100 or more
cycles to get information back from
Projections for transistor size and die integration capacity.
Year
Feature size (nm)
integration Capacity (bt)
2004
90
2
2006
65
4
2008
45
6
2010
32
16
2012
22
32
a But one only really gets double the performance if they can figure out how to keep all of
those cores busy.
main memory—hence, the focus by architects on cache memory systems that
tackle this “memory wall.” And multicore parts put even more pressure on
the DRAM, demanding more capacity,
lower latencies, and better bandwidth.
As pointed out in the following paper by Lee, Ipek, Mutlu, and Burger,
DRAM memory scaling is in jeopardy,
primarily due to reliability issues. The
storage mechanism in DRAMs, charge
storage and maintenance in a capacitor, requires inherently unscalable
charge placement and control. Flash
memories, which have the advantage
of being nonvolatile, have their own
scaling limitations. Thus, the search
for new main memory technologies
has begun.
The authors make a case for phase
change memories (PCMs) that are
nonvolatile and can scale below
40nm. PCMs store state by forcing a
phase change in their storage element
(for example, chalcogenide) to a high
resistance state (so storing a “0”) or
to a low resistance state (so storing a
“ 1”). Fortunately, programming current scales linearly. However, PCMs
do not come without their disadvantages: read and, especially, write latencies several times slower than DRAMs,
write energies several times larger
than DRAMs, and, like Flash, a limited
lifetime directly related to the number
of writes to a memory location.
This paper is a wonderful illustra-
tion of the way computer architects
can work around the limitations of the
technology with clever architectural
enhancements—turning lemons into
lemonade. By using an area-neutral
memory buffer reorganization, the
authors are able to reduce application
execution time from 1.6X to only 1.2X
relative to a DRAM-based system and
memory array energy from 2.2X to 1.0X
also relative to a DRAM-based system.
They use multiple, narrower memory
buffers, which reduces the number of
expensive (in terms of both area and
power) sense amplifiers and focus on
application performance rather than
the performance of an individual
memory cell.
Mary Jane Irwin ( mji@cse.psu.edu) is evan Pugh
Professor and A. Robert noll Chair in engineering in the
Department of Computer science and engineering at
Penn state university, university Park, PA.