figure 2. superscalar processor augmented with recording
Reg free list
Instruction footprint scan out
path after system failure
Reg alias table
Phys. reg file
Instruction footprint flow
Reg alias table
2. An ID (identification) assignment unit responsible for
assigning and appending an ID to each instruction
that enters the processor.
3. A post-trigger generator, which is a mechanism for
deciding when to stop recording.
While an instruction, with an ID appended, flows through
a pipeline stage, it generates an instruction footprint corresponding to that pipeline stage which is stored in the
recorder associated with that pipeline stage. An instruction
footprint corresponding to a pipeline stage consists of
1. The instruction’s ID that was appended
2. Auxiliary information (Table 2) that tells us what the
instruction did in the microarchitectural blocks con-
tained in that pipeline stage
Synthesis results (using Synopsys Design Compiler with
TSMC 0.13 microns library) show that the area impact
of the IFRA hardware infrastructure is 1% on the Illinois
Verilog Model24 assuming a 2MB on-chip cache, which is
108 communicAtions of the Acm | FEbrUary 2010 | VoL. 53 | No. 2
table 2. Auxiliary information for each pipeline stage. the 2-bit and
3-bit residues are obtained by performing mod- 3 and mod- 7 operations
on the original values, respectively.
2-bit residue of
Issue 3-bit residue of
AlU, MUl 3-bit residue
of result; Memory
Commit Fatal exceptions 4
Total storage required for all recorders: each
entry contains an additional 8-bit instruction
Id (explained later).
typical of current desktop/server processors. The area cost is
dominated by the circular buffers present in the recorders.
Interconnect area cost is relatively low because the wires connecting the recorders (Figure 2) operate at slow speed, and
a large portion of this routing reuses existing on-chip scan
chains that are present for manufacturing testing purposes.
2. 1. iD-assignment unit
For the recorded data to be useful for offline analysis, it is
necessary to identify which of the trillions of instructions
that passed through the processor, produced each of the
recorded footprints. Hence, each footprint in a recorder
must have an identifier or ID.
Simplistic ID assignment schemes have limited applicability. For example, assigning consecutive numbers to each
incoming instruction, in a circular fashion, using very wide
IDs is wasteful: using 40-bit IDs will increase the instruction footprint total storage to 160KB from 60KB. When IDs
are too short, e.g., 8-bit IDs if there can be only 256 instructions in a processor at any one time, aliasing can occur for
processors supporting out-of-order execution and pipeline