a VaX-11/780 from 1983 with 16mB of Ram, and the ethernet interface containing a motorola 68000 processor to handle the network traffic.
PhotograPh by Patrick finnegan
by the application program. When the
read for the payload data happens, it
is copied from the socket buffer into
application process memory to be digested as required. That makes a total
of four passes over the data in a single
packet before the application gets a
shot at using it. When networks were
slow compared with memory bandwidth and processor speed, the data-copy inefficiency was considered minor compared with the joy of a working
network stack, so it failed to provoke
immediate improvement.
This base-case platform appears
to be the origin of the folk theorem
that “TCP needs one (VAX-)MIPS per
10 megabits/second of network performance.” The 10Mbps Ethernet can
deliver about a megabyte/second of
payload, so this is consistent with the
other folk theorem of “one megabyte
of memory per MIPS per megabyte of
I/O.” Where this came from is difficult
to pin down, but it is frequently credited to Gene Amdahl.
Now, let’s move this same model
to PC hardware. For a long time, one
of the principal distinctions between
PCs and minicomputers was I/O performance. To be brutal, compared
with its minicomputer forebears, the
PC platform started life with almost
no I/O capabilities. Over the life of the
PC platform, that conspicuous lack
prompted major renovations of the
PC’s I/O architecture. For the period of
our interest, that progressed from the
16-bit ISA bus, to 32-bit PCI, and now
PCI Express. For reasons too boring
to explore here, for a very long time,
packets moved from PC Ethernet cards
into protocol processing buffers with a
byte-copy operation performed by the
CPU, upping the data-handling pass
count to five.
The first significant improvement
came when the raw-packet copy operation and TCP checksum were combined. Some network code tried to
do this in software. As PCI Ethernet
