slice controller for this basic round robin scheduler.
The Mojo IDE comes with code for simulating a CPU.
There are some assembly-like instructions, which are
provided, but any assembly-like instructions can be
defined for a given application. Paired with a round robin
scheduler and external clock, this is a test environment for
haptic t wo-job logical concurrency.
There are additional files needed, which are also in the
XRDS github repository: modified_cpu.luc, modified_
instRom.luc, modifiedcpu_mojo_top.luc, and sliceclock.ucf.
For this project, the majority of instRom.luc and
cpu.luc were left intact. In modified_cpu.luc and modified_
instRom.luc, the major changes were to allow a CPU to
emulate logically concurrent behavior; it can be active or
inactive and raises a “complete” flag. All the scheduling
was added to modifiedcpu_mojo_top.luc. T wo CPUs are
created and then managed with respect to an external
signal from PIN1. The constraints file sliceclock.ucf is
nearly identical to pinIn.ucf.
Once loaded, the FPGA will illuminate the first LED if
job1 completes first, or it will illuminate the second LED
if job2 completes first. But when both jobs are complete,
all eight LED’s will illuminate. If no external circuit is
interfaced, the first LED will light and nothing else will
happen because job2 can never be active. When PIN1 has
voltage, job2 executes, and if PIN1 doesn’t have voltage,
job1 executes. If a circuit is interfaced, then all eight LED’s
will illuminate instantly. This is because the instRom
programs are short compared to the speed of the FPGA. A
further step would be to run more substantial programs
with this test environment.
When engineering or doing computer science at the hardware level, there is an option to gain intuition about your
system haptically, and there is an option to develop controls for your system externally. To do so requires developing an interdisciplinary knowledge of electronics. All code
presented is available in the XRDS github. Happy hacking!
To replicate what was done here (and specifically for
the Mojo v3), all that is required is opening a new project
(“From Example,” “Blinker Demo,” or “Basic CPU”) and
making the modifications.
Alexander DeForge is a student at the University of Maryland University College, studying
computer science. He is primarily interested in systems, including operating systems,
computer networking, and other low level applications.
DOI: 10.1145/3155224 Copyright held by author.
built differ, but not fundamentally.
The completed circuit, which was interfaced with the
FPGA, has a variable clock rate by way of the potentiometer.
Each clock tick can both be seen with an LED, and heard
from a simple speaker, and depressing a button makes the
circuit live. Tapping voltage from the same spot as an LED
is how you extract the clock signal from this circuit. All
that is required is an extra wire rooted at that spot with the
other lead placed into one of the FPGA pinholes.
A PROOF OF CONCEP T
The Mojo v3 was the development board used for this
project. The following is a disclaimer. These devices can be
expensive, and having the ability to download the necessary software to develop on these devices is not straightforward. For the Mojo v3, there is no open source development
alternative, and obtaining licensure with Xilinx to be able
to build projects with Embedded Micro’s IDE will be an
obstacle for some due to legal reasons. When deciding on
a development board, it is recommended to follow through
on all steps to be able to develop for the chip, up until actually loading a ROM onto the FPGA, before you buy.
The Mojo v3 contains the Spartan- 6 FPGA chip. The
hardware definition language (HDL) Lucid was used in the
embedded micro Mojo IDE version B1.3.6. Programming
at this level involves using signals, whose state does not
persist bet ween clock cycles, and flip-flop gates, whose
state does persist between clock cycles. Both are accessed
as bit values or arrays of bit values.
The applicable files for this tutorial are modified_
blinker.luc, modifiedblinker_mojo_top.luc, and pinIn.ucf,
which are located in the XRDS github repository at:
Once loaded into the FPGA, the built-in LED’s will now
blink in unison with the clock signal from the astable
multivibrator. The main changes were to the blinker.luc
and pinIn.ucf files. In pinIn.ucf, the FPGA is instructed
to access PIN1 on the development board. In modified_
blinker.luc, the FPGA is instructed to treat PIN1 as an input
signal. That input signal controls a case statement with two
cases, one for voltage and one for no voltage. In this setup,
each case sets the built-in LED’s to on or off.
What we now have is an external variable-interval clock and
software that supports alternatively executing two sets of
code—the two cases. User-controlled logical concurrency
can be emulated in this FPGA for exactly t wo jobs. The external variable-interval clock can be used as a haptic time
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