Figure 2. INVFO4 energy vs. delay for various technology nodes and devices;
the initials BCB or MASTAR appear after each device to indicate the computation
model for the data point.
15nm Thin-TFET (BCB)
15nm HetJTFET (BCB)
15nm CMOS HP (BCB)
45nm CMOS HP (MASTAR)
15nm CMOS LV (BCB)
15nm GaNTFET (BCB)
22nm CMOS HP (BCB)
32nm CMOS HP (BCB)
45nm CMOS HP (BCB)
no longer valid when transitioning
from CMOS to beyond-CMOS devices.
Here, we describe three modifications—one for each scaling model—
required for benchmarking beyond-CMOS devices.
First, in the DS-device-scaling model, we derived CMOS frequency- and
power-scaling factors by normalizing
INVFO4 frequency and power data for
each technology node against 45nm
CMOS data (2010 column in the 2010
ITRS9).b As the 45nm frequency and
power data are based on MASTAR IN-
VFO4 simulations, simply normalizing
the 15nm BCB-based frequency and
b The 45nm power input was analytically computed as Pdynamic = αCV2 f (where α = 1) using the
same data as the 2010 ITRS report.
on parallel applications, or PARSEC, 2
for each such node. This DS model
spans from the device level to the architectural level and includes a device-scaling model, a core-scaling model,
and a multi-core-scaling model.
The device-scaling model considers trends associated with device scaling, including area, frequency, and
power, from 45nm to 8nm, based on
optimistic9 and conservative5
projection schemes.a For each technology
node, scaling factors for frequency
and power are derived by normalizing
their projections against empirical
45nm CMOS data. It is important to
note here that frequency-scaling factors derived from the International
Technology Roadmap for Semiconductors (ITRS) projections are based
on INVFO4 simulations from the
Model for the Assessment of CMOS
Technologies and Roadmaps (
MASTAR) for each technology node. 9 In
this sense, the DS model uses INVFO4
delay to determine the clock frequency of a multi-core processor.
The core-scaling model provides
projections for the maximum performance a single core can achieve for a
given area. Moreover, it also projects
core power for selected core performance. It is derived by creating two scatter plots—core area vs. performance
and core power vs. performance—
using empirical 45nm processor data.
For both plots, SPECmark is used as a
measure of performance, representing aggregate performance of the SPEC
benchmark suite. 24 The authors then
plotted the Pareto-optimal frontier for
processors based on 45nm technology. For each technology generation,
the scaling factors derived in the device
model were then used to scale the area
vs. performance and power vs. performance Pareto frontiers. The result is
a set of processor core projections for
each technology node.
The multi-core-scaling model investigates two multi-core configurations based on CPUs and GPUs, and
four topologies for each configuration—symmetric, asymmetric, dynamic, and composed multi-core.
For a selected multi-core configura-
a 45nm was the current technology node (2009)
when H. Esmaeilzadeh et al. 7 were developing
the original Dark Silicon model.
tion and topology, the DS model uses
the core-scaling model to analytically
compute the best possible speedup,
optimal number of cores, and fraction of dark silicon for each PARSEC
benchmark, given a certain chip area
and TDP budget.
NDS Methodology and
Like the DS model, our nDS model
consists of a device, a core, and multi-core-scaling models. However, as the
models are based on CMOS scaling
trends, they cannot be utilized directly for beyond-CMOS devices without
accounting for the change in device
technology. This is due to the fact that
some of the assumptions (such as Pollack’s Rule) made in the DS model are
Figure 3. Erroneous compression of the 45nm area vs. performance Pareto frontier
occurs when a device has a frequency-scaling factor of less than one, assuming
beyond-CMOS devices and CMOS are of equal size.
10 20 30 40 50 60 70 80
CMOSLV GaNTFET HetJTFET
CMOS HP 45nm
CMOS HP 15nm
CMOS HP 45nm
CMOS HP 15nm
CMOS LV 15nm
HetJ TFET 15nm
Thin- TFET 15nm