mately, we want to determine if beyond-CMOS devices can overcome the
growth of dark silicon and provide a
future path for the continuation of
Devices and Benchmarking Models
First, we briefly introduce our selected beyond-CMOS devices and their
parameters used in our case study.
We then summarize the BCBv319 and
Dark Silicon7 models that are the
foundation of our framework.
Overview of steep-slope devices.
From the classes of beyond-CMOS de-
vices, we selected four representative
“steep slope” devices that initial de-
vice/circuit-level benchmarking efforts
suggest are among the most competi-
tive with CMOS. 19 Specifically, we se-
lected the heterojunction III-V TFET
(HetJTFET), 21 Negative Capacitance
FET (NCFET), 20 gallium nitride TFET
(GaNTFET), 16 and two-dimensional
hetero-junction interlayer TFET (Thin-
TFET). 14 Steep-slope devices offer a
sub-threshold slope below the intrin-
sic limit for CMOS of 60mV/decade.
The result is increased on-current
and reduced-leakage current at low-
supply voltage when compared to
CMOS. Table 1 reports the CMOS and
steep-slope device parameters used
in our model.
BCB overview. The first beyond-CMOS benchmarking effort by Bernstein et al., 1 BCBv1, which evolved
from Phase 1.0 of the Semiconductor
Research Corporation’s Nanoelec-tronics Research Initiative, aimed to
assemble device researchers to collectively benchmark their devices.
However, due to a lack of unifying
benchmarking guidelines, no conclusive argument could be made from
the device comparisons. To overcome
this lack of guidelines, Nikonov and
Young18 developed an analytical methodology built on BCBv1, or BCBv2,
by which all device parameters for a
given device class would be derived
from the same uniform assumptions,
relations, and schemes. These computations yielded estimates for performance, area, switching delay, and
energy. BCBv319 was released in 2015
to reflect an improved understanding
of beyond-CMOS devices and their operations. In addition to updated device parameters, BCBv3 also included
new logic-circuit configurations (such
as sequential logic) and computation
of standby power for each device.
Figure 1 is a sample output of BCBv3
comparing dynamic switching energy
vs. delay of CMOS and our selected
devices for an inverter fanout-of- 4
(INVFO4), a circuit used to estimate
input/output signal delay.
Dark silicon model overview. In
2011, Esmaeilzadeh et al. 7 explored
multi-core scaling limits for five tech-
nology-node generations (45nm to
8nm) to project how core scaling might
affect the performance (measured in
SPECmarks) of multi-core processors.
They developed an analytical model to
compute potential performance gains
the circuit level. The second is an ar-
chitectural-level approach called the
“Dark Silicon,” or DS, model, that ex-
plores the limits of multi-core scal-
ing within a fixed TDP and area bud-
get for CMOS-based technology. 7
Combining these two methodolo-
gies and introducing three modifica-
tions, we were able to benchmark
beyond-CMOS devices at the archi-
tectural level for multi-core proces-
sors executing parallel workloads, or
PARSEC benchmarks. 2 To investi-
gate the state of the art, we input
four promising beyond-CMOS devic-
es to nDS and quantified their per-
formance and percentage of dark
silicon with respect to CMOS. Ulti-
Figure 1. BCBv3 sample output showing dynamic energy vs. delay of an inverter INVFO4
for various device technologies; device input parameters are reported in Table 1.
Heterojunction III-V TFE T
Negative Capacitance FET
Gallium Nitride TFET
2D Heterojunction Interlayer TFET
Table 1. Benchmarking parameters for CMOS and steep-slope devices.
Device VDD (V) IOn (µA/µm) CG, avg (fF/µm)
CMOS HP9 0.73 1,805 0.41
CMOS LV10 0.3 53 0.06
HetJTFET21 0.4 417 0.21
NCFET20 0.4 1,324 0.75
GaNTFET16 0.2 47 0.34
Thin-TFET14 0.2 263 0.18
Geometric Parameters [ 19]
Half-pitch (nm) EOT (nm) Gate Length (nm) Gate Width (nm)
15 1.08 12. 8 60
We gathered device parameters from the indicated references in the leftmost column.
Relevant parameters for each device are supply voltage (VDD), on-current (IOn),
average gate capacitance (CG, avg), metal half-pitch, equivalent oxide thickness (EOT),
gate length, and gate width.