MANY PROCESSORS EXPOSE performance-monitoring
counters that help measure ‘productive performance’
associated with workloads. Productive performance is
typically represented by scale factor, a term that refers
to the extent of stalls compared with stall-free cycles
within a time window. The scale factor of workload is
also influenced by clock frequency as
selected by frequency-selection governors. Hence, in a dynamic voltage/fre-quency scaling or DVFS system (such as
Intel Speed Shift1), the utilization, power, and performance outputs are also
functions of the scale factor and its variations. Some governance algorithms do
treat the scale factor in ways that are native to their governance philosophy.
This article presents equations that
relate to workload utilization scal-
ing at a per-DVFS subsystem level.
A relation between frequency, utili-
zation, and scale factor (which itself
varies with frequency) is established.
The verification of these equations
turns out to be tricky, since inherent
to workload, the utilization also varies
seemingly in an unspecified manner at
the granularity of governance samples.
Thus, a novel approach called histo-
gram ridge trace is applied. Quantify-
ing the scaling impact is critical when
treating DVFS as a building block. Typ-
ical application includes DVFS gover-
nors and/or other layers that influence
utilization, power, and performance of
the system. The scope here though, is
limited to demonstrating well-quanti-
fied and verified scaling equations.
Intel has three architecture-inde-pendent registers that are relevant to
Article development led by
Workload scalability has a cascade
relation via the scale factor.
BY NOOR MUBEEN