Because all of these methods are
essentially vertical stacks of 2D devices, they are often called 2.5D. True
3D, in the view of some, requires a
single, monolithic integrated circuit.
In these, devices are built on top of interconnects using integrated circuit
fabrication technology, rather than
stacking chips or wafers and connecting them with TSVs.
The advantage of monolithic integrated circuits is that the interconnects are much denser than they are
with TSVs because the area needed
to make a connection, in the order
of 60 nanometers, is about 100 times
smaller, says Stanford’s Wong. Samsung and MonolithIC 3D, for example, have built very high-density 3D
But monolithic 3D technology is
in its infancy. A layer of transistors
is made, they are connected by wires,
then another layer of transistors is
put down, and so on upward. The
biggest problem is that the processing of subsequent layers is so hot—
above 400 Celsius—that it can melt
the wires below. That presently limits the number of layers to just two or
three, Wong says.
Wong and colleagues at Stanford
have built a monolithic 3D field-
show their strength
devices and dense
programmable gate array (FPGA).
The monolithic 3D FPGA is built in a
single complementary metal–oxide–
semiconductor (CMOS) wafer, but
has two layers. Wong’s initial FGPA
had a second layer of nonvolatile resistive RAM, or RRAM, which does not
use transistors, but he is now working
on a FGPA that has a second layer of
transistors followed by a third layer of
Monolithic integrated circuits
are a good way to make such hybrid
chips, using materials that are higher
performing than CMOS, Wong says.
“You can imagine,” he says, “integrat-
ing indium phosphide or gallium ar-
senide on top of silicon.”
Stacking of 2D chips is the best
method when the designer has many
layers of relatively simple, uniform
devices, like memories. Monolithic,
on the other hand, shows its strength
with complex devices and dense inter-
A Radically Different
Wojciech P. Maly, a professor of electrical and computer engineering at Carnegie
Mellon University, has come up with an idea he calls the Vertical Slit Fe T (field-effect
transistor), or VeSFe T. it is a junctionless, twin-gate transistor placed vertically
between the layers of a 3D integrated circuit. The device consists of four parallel
metal “pillars,” arranged around a vertical silicon slit, with two opposite pillars
comprising the two gates and the other pillars serving as the current source and
drain. The silicon slit in the middle of the four pillars acts as a “valve” controlling the
flow of current between the source and drain and switching the state of the two gates.
VeSFe Ts can be strung together endlessly in thin layers of transistor “canavases,”
and then stacked in regular patterns, says Maly, who has built proof-of-concept
prototypes with a Singapore company.
any of the four metal pillars can act as a communication channel directly through
the transistor to layers above and below, whereas in traditional 3D devices the
transistors in different layers must communicate via the thicker and longer through
silicon vias (TSVs). in the case of VeSTiCs, each pillar has two terminals, lower and
upper, enabling communication for the signal and power distribution networks.
“Communication is built right into the transistor, so i don’t have to build extra [vias]
for that,” he says.
The key attributes of the resulting structure are its simplicity and regularity,
according to Maly. Unlike a TSV-based 3D integrated circuit, an integrated circuit
based on this technology will be far easier to build and test. The metal pillars
also allow for faster heat transfer out of the chip. Moreover, the simplicity and
homogeneity offer a measure of fault-tolerance, since a defective transistor can be
easily bypassed in favor of an identical structure nearby.
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and test circuits, D43D: 2nd Design for 3D
Silicon Integration Workshop, Lausanne,
Switzerland, May 26–28, 2010.
Garrou, P., Lu, J.J.-Q., and Ramm, P.
Three-Dimensional Integration, Handbook
of Wafer Bonding, Wiley-VCh Verlag & Co.,
Weinheim, Germany, 2012.
Liauw, Y., Zhang, Z., Kim, W.,
El Gamal, A., and Wong, S.
nonvolatile 3D-FPGA with monolithically
stacked RRAM-based configuration
memory, 2012 IEEE International
Solid-State Circuits Conference Digest
of Technical Papers, San Francisco, CA,
Feb. 19–23, 2012.
Maly, W., et al.
Twin gate, vertical slit FET for highly
periodic layout and 3D integration,
Proceedings of the 18th International
Conference Mixed Design of Integrated
Circuits and Systems, Gilwice, Poland,
June 16–18, 2011.
Wong, S. and El Gamal, A.
The prospect of 3D-IC, IEEE Custom
Integrated Circuits Conference, San Jose,
CA, Sept. 13–16, 2009.
Gary Anthes is a technology writer and editor based in
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