Technology | DOI: 10.1145/2330667.2330673
Chips Go upscale
After decades in Flatland, the end of Moore’s Law
is pushing semiconductors into the third dimension.
FOr 50 yearS, semiconductor chips have been essentially flat devices, with transistors laid down in greater and greater densities. The way to
keep riding Moore’s Law was to make
transistors ever smaller and closer
together in a plane. Now, such miniaturization has been slowed by the difficulty of managing power consumption and heat, and by the soaring cost
Chips are made by projecting a circuit design onto a flat silicon surface,
then using a photochemical process
to etch the circuits into the silicon.
But as the circuit features get smaller
and smaller, they begin to “leak” current, which wastes power and produces heat. Although no one knows just
where the limit lies, it seems likely
the shrinkage of conventional silicon
transistors will eventually end.
The industry’s answer to the power
and cost problems has become 3D,
building electronic devices upward as
well as outward. The principle is simple and even obvious, but reliable and
affordable manufacturing remains
difficult. Many variations on the 3D
theme have emerged, but there are
three basic approaches, sometimes
referred to as 3D packaging, 3D integration, and monolithic integration.
Although now in limited production, 3D chips and packages of various types will become common in the
market over the next 10 years, says
Simon Wong, a professor of electrical engineering at Stanford University
who specializes in integrated circuits.
“I believe Moore’s Law will continue
for many more generations, as there
are innovative ideas for scaling devices and mediating power dissipation,”
Wong says. “However, the escalating
manufacturing cost is an issue. 3D
allows continuous improvement in
performance and reduction of power
dissipation at each technology node,
Developed by iBm and 3m, a new type of electronic “glue” can be used to construct stacks
of semiconductors. the glue, shown in blue above, connects up to 100 separate chips and
conducts heat away from the silicon package.
extending the lifespan of each node
beyond three years, and allowing
manufacturers more time to recover
the huge capital investments.
“Instead of continuing to shrink
the transistor, one can design a sys-
tem in the third dimension for similar
levels of performance improvement,”
Wong says. 3D chips will find applica-
tion virtually everywhere but will be
especially attractive in mobile devic-
es, where space is limited.