technical Perspective
Power efficiency as
the #1 Design constraint
By Charles Moore

MooRE’S LAW, 2 AND the associated observations on scaling by Bob Dennard, 1 describe many of the key technical foundations that have given rise to the amazing growth of the modern semiconductor industry. But, taking a step back from these insightful assertions, we can see an even bigger picture emerge related to energy usage and power consumption. The earliest computers, such as the machine envisioned by Charles Babbage in 1822, were mechanical marvels. Although simultaneously amazing and under-appreciated, they certainly set the stage for modern computing era.

As it turns out, these machines consumed very large amounts of power (for the time), and were quickly replaced by more power-efficient, electro-mechanical, relay-based systems. This shift enabled larger machines with more capability, but they too soon hit the practical “power wall” of the time. In 1946, the first vacuum tube-based computers were designed, and once again, these set a new standard in capability and power efficiency for the day, eventually replacing the relay-based systems. This pattern repeated with the invention of the discrete transistor, the integrated circuit, the bipolar-based integrated circuits, and the FET-based integrated circuits. The key point here is that these technology transitions were driven in equal parts by the new capability they brought to light and the improved power efficiency they offered.

That brings us to modern VLSI-
based systems. Once again, our cur-
rent technology of choice, CMOS-
based integrated circuits in particular,
has hit a modern day “power wall.”
There are, of course, lots of highly in-
novative process technology tweaks
and circuit design tricks to extend
the life of the CMOS-based era, but
these are really only buying time until
a fundamentally new technology op-
tion becomes practical. Unfortunate-
ly, although there are several interest-
ing contenders, it doesn’t appear any
of these will be practical within the
next decade.

this paper uncovers
some of the
most significant
differences in power
efficiency between
a general-purpose
processor and a
special-purpose asic.

The power efficiency and performance advantages of special-purpose ASICs versus general-purpose processors in not new, nor is it surprising. In fact, the essence of these differences is reflected in the computer architects’ mantra of “optimizing for the common case.” In the 1968 seminar paper “On the Design of Display Processors” by T.H. Myer and Ivan Sutherland, 3 this trade-off between generality and complexity is particularly well described with relevant examples from that time period. In particular, they observe that the appropriate solution is both application and technology dependent, and from that, they coin the phrase “The Wheel of Reincarnation” to illustrate these shifting optimizations.

But this paper goes a step beyond the general observation and quantitative analysis of a particular application. It also sets the stage for designing future machines that are prepared for higher-level hardware abstractions. This proposal implies some profound implications for application analysis, algorithm design, machine organization, and associated design methodologies. Combined, they may offer improvements in power efficiency, raw performance, and design productivity. This triple play is particularly significant at this point in time, as the industry must simultaneously work around the ongoing CMOS “power wall” while also investing to find that next technology to reset the power-efficiency bar.

 

References

1. dennard, r. et al. design of ion-implanted Mosfets with very small physical dimensions. IEEE Journal of Solid State Circuits SC- 9, 5 (oct. 1974).

2. Moore, g. cramming more components onto integrated circuits. Electronics Magazine, apr. 1965.

3. Myer, t.h., sutherland, i.e. on the design of display processors. Commun. ACM 11, 6 (June 1968).

 

Charles Moore ( [e-mail]) is a corporate fellow at aMd, and the cto for aMd’s technology group.