scription here, but BSV indeed defines
such a concrete mapping of rules into
clocked hardware. Clocks and Resets are abstract data types, and rules
and methods are mapped into clock
and reset domains. Strong static type
checking verifies the isolation of these
domains. In summary, BSV has easy-to-use and semantically rigorous facilities
for the robust creation of designs with
multiple clock domains.
Another very important consideration today is power consumption.
At a fine granularity, BSV clocks can
be gated, with gating conditions integrated organically into rule conditions. At the coarser granularity of IP
blocks, BSV has power-management
facilities to switch off or scale power
and clocks to entire modules or subsystems in a disciplined manner.
One intriguing thought is that BSV
could also be compiled into asynchronous logic (which has many potential
advantages relating to circuit timing
and power consumption), but how to
do this, and how to reason about system performance in this regime, are
still open research questions.
Synthesis quality for ASICs.
Technology to compile Rules into efficient
hardware was first developed more
than a decade ago.
8 It has been improved continuously since then and
has been used on hundreds of designs. In some there was an existing
RTL design for apples-to-apples comparisons, and in general, quality has
been comparable (as measured in silicon area and performance), typically
In a few cases, BSV-generated RTL
has significantly better quality (15%–
25%) than hand-coded RTL. This is
surprising at first because in software
you typically pay a performance penalty
for higher abstraction. As illustrated in
Figure 1, however, higher abstraction
in hardware design can yield significant algorithmic advantages (that is,
more efficient architectures).
Synthesis for FPGA-based simulation. The universal applicability and
synthesizability of BSV has opened
the door for many to use FPGAs as
their standard simulation engine,
from the earliest stages of design,
and with a “design-by-refinement”
Bluespec Inc., by “eating its own
dog food,” has used BSV to create
highly parameterized communica-
tion, debugging, and IP libraries for
FPGA boards. These form a kind of
operating system for FPGAs, so that
the user has high-level facilities for
communicating with a host and de-
bugging a model or design instead of
the customary painful wrestling with
the raw FPGA board hardware.
Historically there has been an almost
total separation between software
and hardware designers, much of it
attributable to the wide cultural (
semantic) gap between the languages
they use to design their respective
systems. Modern systems demand a
reduction or elimination of this specialization. All interesting hardware
systems today must run sophisticated
software, and many complex software
computations must move to hardware to meet performance and power
BSV is an attempt to address this
problem. Rather than trying to force
fit solutions for von Neumann ma-
chines (such as C++ and threads) into
hardware description, BSV has taken
excellent ideas from software that are
naturals for hardware description. It
describes behavior using Rules (from
Term Rewriting Systems), which are
excellent for massive, fine-grain,
heterogeneous, reactive concur-
rency (hardware!). It describes struc-
ture and structural abstraction us-
ing types, overloading, higher-order
functions, parameterization, and
even monads from Haskell. These
ideas have been tested in the field for
well over five years and used in fin-
ished products, one of which might
be in your pocket right now.
SoC: Software, hardware, nightmare, Bliss
George Neville-Neil, Telle Whitney
The Reincarnation of Virtual Machines
Blurring Lines Between
hardware and Software
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Rishiyur nikhil ( firstname.lastname@example.org) worked on haskell
and functional programming languages and compilers for
parallelism, and dataflow and multithreaded architectures
for about 20 years. since 2000 he has been applying those
ideas to hardware design.