The only feasible solution to this problem is what hardware people call emulation, which is simulation of the hardware design on field-programma-ble gate arrays (FPGAs). This FPGA-based emulation cannot be left to final drafts of a design, however; it must begin at the very start of the design process, from early models onward. Doing so places further requirements on the behavioral semantics of HDLs.

Simple emulation is not enough,
however. Previously it might have
been acceptable to use separate high-
level languages for models and test
benches that run only in software
simulation, such as SystemC TLM
(Transaction Level Modeling) 19 and
SystemVerilog VMM (Verification
Methodology Manual). 2 Today, how-
ever, what is needed is an HDL that
can be used for all these purposes—
from early models and test benches
to detailed implementation—where
these different components can be
mixed freely and where all these com-
ponents can be synthesized for FPGA
simulation. Thus, the HDL needs to
be universal, both in the sense that
it is suitable for all kinds of digital
designs (for example, not just signal
processing) and in the sense that it
should be fully synthesizable, wheth-
er used for models, test benches, or
implementations.

Why not use existing software
Language for hardware Design?
Before looking at BSV, it is useful to