practice
Doi: 10.1145/2001269.2001284
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Applying lessons from software languages
to hardware languages using Bluespec
SystemVerilog.
BY Rishi YuR s. nikhiL
abstraction
in hardware
system Design
THE HISToRY oF software engineering is one of
continuing development of abstraction mechanisms
designed to tackle ever-increasing complexity.
Hardware design, however, is not as current. For
example, the two most commonly used hardware
description languages (HDLs)—Verilog and
VHDL9, 12—date back to the 1980s. Updates to
the standards lag behind modern programming
languages in structural abstractions such as
types, encapsulation, and parameterization. Their
behavioral semantics lag even further. They are
specified in terms of event-driven simulators running
on uniprocessor von Neumann machines (and this is
true even for their recent descendents, SystemVerilog
and SystemC10, 11).
These HDLs all have “synthesizable subsets” that
constrain them in an effort to narrow this behavioral
gap, but the mismatch is never completely eliminated.
The strain is beginning to show as
hardware chip capacity has grown exponentially according to Moore’s Law
and we are called upon to design entire
systems-on-a-chip (SoCs) of astonishing diversity and complexity.
Another important issue is that verification (testing) has so far been done
using simulation, but this is decreasingly practical.
3 In modern SoCs, the
hardware is large and complex, and it
runs heavy software loads such as full-featured operating systems and applications. Verification involves simulating all of these together, and it is
not unusual for software simulations
to run for days or weeks. Simulation
speeds are typically cited in the 10s to
100s of KHz, whereas what are needed
are MHz speeds.
