Communications - April 2009

figure 6: flash memory controller architecture. the flash disk cache device driver sends requests to the hardware interface. these requests also specify the ecc strength and density mode of the accessed page. in turn, the controller accesses the flash chip after performing ecc encoding for a write, or decoding for a read. the device driver software receives any requested data along with an indication of the number of failing flash bits.

Flash access request

Flash address and data

Page ECC and Density settings (from Metadata)

BCH
encode /
decode

External interface

NAND Flash

I/O interface

CRC
encode /
decode

Data out

Bit error (yes / no)

Flash density control

Flash data (reads)

changing MLC pages into SLC pages as needed. To show the potential improvement of Flash performance by controlling density, we present a study using real disk traces.

Using disk activity traces from the University of Massachusetts Trace Repository²⁰ for financial and web search applications, we analyzed the average access latency for different SLC/MLC partitions, for several Flash sizes.

A hybrid allocation of SLC and MLC Flash provides minimum access latency, because it is sometimes more effective to store heavily used data in a faster SLC page and lose one page of storage space. Figure 7 shows the average delay (left y-axis) achieved for an optimal partition (right y-axis) between SLC and MLC. The x-axis shows the Flash memory area and extends far enough to contain the entire working set. As expected, when the size of the cache approaches the entire workload, latency reaches a minimum using only SLC cells. Intermediate Flash sizes provide minimum latency through a combination of MLC and SLC with the most frequently accessed data in the faster SLC cells. The best division between SLC and MLC depends on the access frequencies of the data pages. For example, if there are hot pages that are significantly more active than other pages, the bias will be towards SLC. This type of behavior is exhibited by the Financial2 trace (Figure 7(a)) where the SLC allocation grows rapidly with Flash capacity. If the access frequencies are more uniform (e.g., Websearch1 in Figure 7(b) ) it is better to have a bigger (MLC) cache to increase the number of accesses to Flash because going to disk is much slower.

3. 3. operation and dynamic reconfiguration We use a typical software device driver interface to access the Flash memory controller. The driver specifies which Flash address is to be accessed along with the read or write mode. For a write, the driver also sends the new data to the