Second, we show that a programmable Flash memory
controller can improve Flash cell reliability and extend
memory lifetime. The first programmable parameter is
error correction code (ECC) strength. The second is the
Flash cell density—changing from multilevel cells
(MLC) to single-level cells (SLC).
figure 2: (a) example dual-mode SLc/mLc flash bank organization
and (b) time spent in garbage collection as a function of the flash
space in use.
2. 1. Properties of a nAnD flash device
Flash memory is a nonvolatile memory device that can be electrically read, written, and erased. Flash memory cells in NAND
Flash are connected in series to maximize cell density. Further,
to improve Flash density, each Flash memory cell can use multiple threshold voltage levels to store more than one bit per
cell. NAND Flash supporting MLC is called MLC NAND Flash.
NAND Flash using a single threshold voltage level (technically
two levels) is called SLC NAND Flash. Cutting-edge MLC NAND
Flash supports 4 bits per cell. There are significant differences
in the access time and lifetime of the two types. Although MLC
Flash is cheaper and bit density is higher relative to SLC, MLC
is slower to read and write and has shorter lifetime by a factor
of 10 or more. Typical latencies for read, write, and erase are
25 µs, 250 µs, and 0.5 ms for SLC and 50 µs, 900 µs, and 3. 5 ms
for 2-bit MLC. The gap between performance and lifetime is
getting worse as the number of bits per Flash cell is increased.
This may be perfectly acceptable for some applications; for
example, a tune in an MP3 player may only be replaced every
few days. A disk cache, however, may have all of its locations rewritten several times a day depending on the amount of disk
traffic and size of the cache.
NAND Flash is organized in units of pages and blocks. A typi-
cal Flash page is 2KB in size and a Flash block is made up of 64
Flash pages (128KB). Random Flash reads and writes are per-
formed on a page basis and Flash erasures are performed per
block. A Flash must perform an erase on a block before it can
write to a page belonging to that block. Each additional write
must be preceded by an erase. Therefore out-of-place writes are
commonly used to mitigate wear-out. These writes append new
data to the end of the log while old data pages are invalidated.
NAND Flash can also be dynamically configured to support multiple Flash memory cell types for each page or
block. In fact, such devices are now commercially available,
e.g., Samsung’s Flex-OneNAND. Figure 2(a) illustrates the
organization of an SLC/MLC dual-mode device. Pages in
SLC mode consist of 2048 bytes of data area and 64 bytes of
“spare” data for ECC bits. When in MLC mode, an SLC page
can be split into two 2048 byte MLC pages. Pages are erased
together in blocks of 64 SLC pages or 128 MLC pages.
When the number of faulty bits per block exceeds the capabilities of an ECC, blocks are disabled, reducing the capacity
of the memory. This is an instance of wear-out affecting system
performance over time, especially, for file cache applications.
MLC Flash ages quicker than SLC Flash. An MLC Flash
can support fewer reliable write/erase (W/E) cycles due to the
smaller threshold voltage margins between bit values. New
Flash architectures6 can circumvent this problem by switching from high-density MLC to lower density or even single-level mode to counter wear-out. No policy currently exists to
1 block = 64 SLC/128 MLC pages
(a) Flash block diagram
20% 40% 60% 80%
Used flash space
perform the mode selection, so we propose a mechanism for
changing mode, tailored to a disk caching application.
Because Flash blocks have a limited number of erases
before they develop faulty bits, a wear-leveling algorithm
attempts to equalize the number of erases performed on
3 This has to be achieved without performing
more erases than necessary. The simplest method of wear-leveling is to treat the device as a circular log. New data is
written to the next available page and the old page is invalidated. However, wear-leveling causes fragmentation problems. Fragmentation is addressed with garbage collection.
The process of garbage collection reads valid pages from
erase blocks containing some invalid pages, then writes
them to a previously erased block.
4 Garbage collections free
up pages that are ready to write new data. This process takes
time and increases the amount of wear in the Flash blocks.
The overhead in garbage collection increases as less
free space is available on Flash. This becomes a significant
aPril 2009 | Vol. 52 | no. 4 | communicAtionS of the Acm